This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-179014, filed Jun. 13, 2001, the entire contents of which are incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which includes MISFET (insulated gate field effect transistor) and Schottky barrier diode (SBD) on a single semiconductor chip, and which is for use in, for example, a synchronization rectifier circuit.
2. Description of the Prior Art
As a power semiconductor device, a MISFET with a vertical structure for flowing a large current in a vertical direction of the semiconductor substrate, an IGBT driven by a MIS gate, etc have been utilized. As the gate structure of the power MISFET used when a breakdown voltage of, for example, about 30-40 V is needed, a planar structure and trench structure are widely known. In the planar structure, a flat gate electrode is used. In the trench structure, a gate electrode is buried in a trench to employ the sidewall of the trench as a channel region, in order to achieve a fine and low-loss structure.
The power MISFET with the trench structure has a number of juxtaposed MISFET cells in the semiconductor substrate. This structure is considered more advantageous than the power MISFET of the planar structure in that the performance can be enhanced (the loss can be reduced) simply by reducing the channel resistance.
The MISFET can be used as a step-down synchronization rectifier DCxe2x80x94DC converter circuit that is for use in, for example, a portable electronic device for efficiently converting a high DC input voltage into a low DC output voltage.
FIG. 8 shows an example of a connection relationship between the synchronization rectifier circuit and the load circuit.
In this case, an NMISFET as an xe2x80x9cHxe2x80x9d side transistor Q1 is connected between a DC power supply (not shown) and output terminal OUT, a Schottky barrier diode (SBD) 80 is reversely connected between the output terminal OUT and a ground potential GND, and an NMISFET as an xe2x80x9cLxe2x80x9d side transistor Q2 for switching is connected in parallel with the SBD 80. Each of the parasitic PN-junction diodes D1 and D2 is provided between the source/drain of a corresponding one of the transistors Q1 and Q2. Further, an inductor such as a coil L, serving as a load circuit, and a smoothing capacitor C are connected in series between the output terminal OUT and ground potential GND.
As well known, in the synchronization rectifier circuit shown in FIG. 8, the xe2x80x9cHxe2x80x9d side transistor Q1 is intermittently and cyclically driven by a pulse signal having a duty ratio controlled in accordance with a desired output voltage, thereby providing the desired output voltage to the smoothing capacitor C.
While the xe2x80x9cHxe2x80x9d side transistor Q1 for load driving is in the ON state, a driving current is supplied from the DC power supply to the load circuit (coil L) via the xe2x80x9cHxe2x80x9d side transistor Q1, thereby accumulating energy in the coil L. During the time from when the xe2x80x9cHxe2x80x9d side transistor Q1 has been turned off, to when xe2x80x9cLxe2x80x9d side transistor Q2 has been turned on, the energy accumulated in the coil L (counterelectromotive force) is discharged from the ground potential GND via the parasitic PN diode D2 of the xe2x80x9cLxe2x80x9d side transistor Q2 and the SBD 80. This parallel connection of the transistor Q2 and SBD 80 reduces the power loss.
If the xe2x80x9cLxe2x80x9d side transistor Q2 and SBD 80 are formed on different chips and assembled in different packages, the degree of freedom of design is limited in cost, mount area (occupied space), etc.
Further, if the xe2x80x9cLxe2x80x9d side transistor Q2 and SBD 80 are formed on different chips, and are mounted on a single lead frame in an electrically separated condition, it is necessary to connect, using an external wire, between the source of the transistor Q2 and the anode of the SBD 80, and also between the drain of the transistor Q2 and the cathode of the SBD 80 (for example, to connect them to the lead frame by wire bonding), thereby increasing the resistance or inductance component of the entire circuit.
For eliminating the necessity of connecting the transistor Q2 and SBD 80 by the external wire to reduce the cost, the mount area and the resistance or inductance component of the wiring layer, an NMISFET/SBD-mounted semiconductor device has been proposed, in which the transistor Q2 and SBD 80 are provided on a single semiconductor chip, and the source and drain electrodes of the transistor Q2 are made to also serve as the anode and cathode of the SBD 80, respectively.
FIG. 9 illustrates perspectively an example of a pattern layout on a chip employed in the conventional NMISFET/SBD-mounted semiconductor device.
On a semiconductor chip 40, an SBD is provided in an SBD-forming region 44 (indicated by the broken line in FIG. 9) that is a part of the FET-forming region for forming an NMISFET. On the top surface of the chip, a first common main electrode 41, which serves as both the source electrode of the NMISFET and the anode of the SBD, is provided, and the surface gate electrode 42 of the NMISFET is provided, isolated from the first main electrode 41 by an insulation film 43. On the reverse surface of the chip, a second common main electrode (see FIG. 10), which serves as both the drain electrode of the NMISFET and the cathode of the SBD, is provided.
FIG. 10 is a schematic sectional view taken along line Xxe2x80x94X of FIG. 9.
Specifically, it shows several NMISFET cells of the trench gate structure and an SBD provided on an N+/Nxe2x88x92 substrate that is obtained by growing an epitaxial Nxe2x88x92 layer on an N+ semiconductor substrate.
In FIG. 10, reference numeral 50 denotes a semiconductor substrate, reference numeral 51 an Nxe2x88x92 layer (epitaxial layer), reference numeral 52 a P base layer formed in the Nxe2x88x92 layer in the FET-forming region, and reference numeral 53 N+ source regions in the P base layer. Further, gate trenches extend from the surfaces of the N+ source regions 53 to the Nxe2x88x92 layer 51.
Reference numeral 55 denotes a gate insulation film provided on the inner wall of each gate trench, and reference numeral 56 a trench gate electrode made of doped polysilicon and buried in each trench gate. Polysilicon wiring layer (not shown) extends from each trench gate electrode to a position away from the gate trench array.
Reference numeral 57 denotes a guard ring region formed in the Nxe2x88x92 layer along the entire (or part of the) peripheral portion of the chip, and an island-shaped SBD-forming region 58 is provided between the guard ring region 57 and FET-forming region 54.
Reference numeral 59 denotes an interlayer insulation film provided on the substrate in the FET-forming region, and contact holes are formed in predetermined portions of the film. Reference numeral 61 denotes an oxide film provided on the portion of the substrate that includes part of the guard ring region 57.
A barrier metal 62 is continuously provided over part of the guard ring region 57, the Nxe2x88x92 layer 51 in the SBD-forming region 58, part of each N+ source region 53, and part of the P base layer 52.
The aforementioned first main electrode 41 made of a metal (such as aluminum), which serves as both the SBD anode and FET source electrode, is provided on the barrier metal 62. Further, the surface gate electrode 42 (see FIG. 9) is provided on the polysilicon gate wiring layer (not shown) in the FET-forming region 54, and is isolated from the first main electrode 41 by the interlayer insulation film 43 (FIG. 9).
Furthermore, on the reverse surface of the chip, the aforementioned second common main electrode 45, which serves as both the FET drain electrode and SBD cathode, is provided.
In the above-described NMISFET/SBD-mounted semiconductor device, the drain current flowing from the FET drain electrode (second main electrode 45) to the source electrode (first main electrode 41) can be ON/OFF controlled using a control voltage applied to the surface gate electrode 42.
Specifically, when a predetermined control voltage is applied to the surface gate electrode 42 with a predetermined voltage applied between the drain and source electrodes of the FET, a drain current flows through an inversion layer formed on the surface portion (channel region) of the P base layer that abuts against each gate trench. Since at this time, a reverse bias voltage is applied to the SBD (denoted by reference numeral 80 in FIG. 8), the SBD is in the OFF state.
When the supply of the voltage to the surface gate electrode 42 is stopped, the FET becomes OFF. If, in this state, a predetermined forward bias voltage is applied between the source electrode 41 and drain electrode 45 of the FET (i.e., between the anode 41 and cathode 45 of the SBD), a forward current flows through the parasitic PN diode (D2 in FIG. 8) of the FET and SBD 80, thereby turning on them.
However, in the above-described semiconductor device, the source electrode 41 of the FET and anode of the SBD are formed of the first main electrode 41, the leak current assumed when the reverse bias voltage is applied between the source electrode 41 and drain electrode 45 of the FET (i.e., the anode 41 and cathode 45 of the SBD 80) is determined by the leak current of the SBD 80, which is inherently relatively large.
Moreover, when the semiconductor chip 40 shown in FIG. 9 is mounted on, for example, a SOP (Small Outline Package) type package, the following problem will occur.
FIG. 11A is a plan view illustrating the arrangement and connection of the semiconductor chip 40 and a lead frame when the semiconductor chip 40 shown in FIG. 9 is mounted on a SOP type package.
FIG. 11B is a sectional view taken along line XIxe2x80x94XI of FIG. 11A.
As shown, the second main electrode 45 on the chip reverse surface is mounted on the bed 71 of the lead frame in such a manner that the surface gate electrode 42 of the FET is positioned closer to the inner leads 72 of the lead frame than to the SBD-forming region 58. Thus, the second main electrode 45 is connected to the drain/cathode terminal (not shown) via the lead frame.
Further, the surface gate electrode 42 and inner lead 72 are bonded by a bonding wire 73, while the first main electrode 41 and inner lead 72 are also bonded by a plurality of bonding wires 73. The reason why a plurality of bonding wires 73 are used to bond the first main electrode 41 to the lead frame is to reduce the wiring resistance and to increase the current capacity. Thus, the surface gate electrode 42 is connected to the gate terminal (not shown) via the outer lead, and the first main electrode 41 is connected to the source/anode terminal (not shown) via the outer lead.
Thereafter, the semiconductor chip 40, and the bed 71, inner leads 72 and bonding wires 73 of the lead frame are covered with a molded resin (not shown), whereby they are packaged and cut into individual semiconductor devices.
As seen from FIG. 11A, the bonding wires 73 connecting the first main electrode 41 to the lead frame are often bonded to the end portion of the first main electrode 41 close to the inner leads 72.
Therefore, since the anode portion of the first main electrode 41 on the SBD-forming region is located at an end remote from the inner leads 72, the electrical resistance of the portion extending from the anode portion to the inner leads 72 will be increased. This will relatively enlarges the voltage drop occurring when a forward current flows to the BSD, thereby putting the electrical resistances of the BSD and each FET cell out of balance. As a result, the characteristics of the FET cells will be unbalanced.
As described above, in the conventional semiconductor device in which the MISFET and SBD are provided on the same semiconductor chip, the source electrode of the MISFET being formed integrally with the anode of the SBD, and the drain electrode of the MISFET being formed integrally with the cathode of the SBD, the leak current flowing when the reverse bias voltage is applied between the source and drain electrodes of the MISFET will be determined by the large leak current of the SBD.
Further, if the semiconductor chip is mounted on the lead frame and packaged, the voltage drop occurring when the forward current flows to the SBD will be relatively large, thereby putting the characteristics of the FET cells out of balance.
A semiconductor device comprising: a first semiconductor layer of a first conductivity type provided on a semiconductor substrate of the first conductivity type; a base layer of a second conductivity type provided in the first semiconductor layer, the base layer defining a vertical MISFET including a plurality of source regions and a gate electrode provided on a gate insulation film; a Schottky barrier diode (SBD)-forming region provided in the first semiconductor layer around the base layer; a guard ring region of the second conductivity type provided around the SBD-forming region; a first main electrode disposed above the first semiconductor layer to cover both the SBD-forming region and the source regions, the first main electrode being provided in common as both a source electrode of the MISFET and an anode of the SBD; a surface gate electrode disposed above the first semiconductor layer to be isolated from the first main electrode by an insulation film, the surface gate electrode being electrically connected to the gate electrodes; and a second main electrode provided in common as both a drain electrode of the MISFET and a cathode of the SBD.